Engineer, Staff – IC Design Job in Andover, Massachusetts US
Tags: andover massachusetts, C, design, design synthesis, digital design experience, Engineer, engineer staff, experienc, experience, Knowledge, Massachusetts, Per, SoC, static timing analysis, timing closure, verification, verification teams, Verilog
In this role you will be responsible for the top-level integration of multi-million gate, leading edge SoC’s.
The engineer will need to gain a solid understanding of the design and design flow in order to integrate IP and support the design during the development phase.
The engineer will also support the physical design team and will be required to make top-level netlist changes in concert with physical requirements.
This person will work with both design and verification teams to validate the design.
Required
1. Detailed digital design experience including RTL design, simulation, and design verificatio
2. Experience with design synthesis using Synopsys Design Compile
3. Logic Equivalence using Formality or Conforma
4. Knowledge of DFT issues including BIST and JTA
5. Verilog, C/C++, Per
6. Strong Design verification experienc
7. Good communication skill
8. The minimum job requirement for this position is BSEE and 6 years of experience or MSEE and 3 years of experience Recommended
1. SoC design experienc
2. High-speed static timing analysis including timing closure and constraint generatio
3. Working knowledge of video standards such as MPEG-2 and H.
264 If interested, please apply online at http://track.
tmpservice.com/ApplyClick.aspx?id=884687-1789-2872
Engineer, Staff – IC Design Job in Andover, Massachusetts US